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Wafer-level Testing and Test During Burn-in for Integrated Circuits

Bahukudumbi, Sudarshan.-Chakrabarty, Krishnendu.

Wafer-level Testing and Test During Burn-in for Integrated Circuits - Artech House, Inc. 2010 - Artech House Integrated Microsystems Series .

ISBN: 9781596939905

Subjects--Topical Terms:
Integrated circuits--Testing.,Integrated circuits--Wafer-scale integration.,Semiconductors--Testing.

Subjects--Index Terms: TECHNOLOGY & ENGINEERING / Electronics / Microelectronics

LC Class. No.: TK7874 .B35 2010

Dewey Class. No.: 621.381

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