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	1.	Wafer-level Testing and Test During Burn-in for Integrated Circuits by Bahukudumbi, Sudarshan.-Chakrabarty, Krishnendu. Series: Artech House Integrated Microsystems SeriesMaterial type: Text Language: English Publication details: Artech House, Inc. 2010Online access: Click here to access online Availability: Items available for reference: VJEC Central Library: Not for loan (1). Add to cart (remove)
	2.	Lab-on-a-chip Techniques, Circuits, and Biomedical Applications by Ghallab, Yehya H.-Badawy, Wael. Series: Artech House Integrated Microsystems SeriesMaterial type: Text Language: English Publication details: Artech House, Inc. 2010Online access: Click here to access online Availability: Items available for reference: VJEC Central Library: Not for loan (1). Add to cart (remove)

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